1. Field of Invention
The present invention relates to a chip package and the packaging process thereof, and particularly to a chip package using a semiconductor substrate as the carrier and the packaging process thereof.
2. Description of the Related Art
Along with constant advances and developments of semiconductor processes, various high-efficiency electronic products have been launched in the market. Thanks to the fast advances in semiconductor processes, the integrity of integrated circuit (IC) devices is continuously higher and higher, too. In the packaging process of an IC device, IC packaging plays a decisive role. In terms of IC packaging type, three types are often used: wire bonding (WB) packaging, tape automatic bonding (TAB) packaging and flip chip (FC) packaging. Each of the packaging types has unique characteristics and applicable fields. In spite of which IC packaging is used, a carrier is always needed within an IC package. The leads on a carrier are electrically connected to bonding pads on the chip, wherein the carrier may be a lead frame or a package substrate.
FIG. 1 is a schematic section view of a conventional flip chip package. Referring to FIG. 1, a conventional flip chip package 100 includes a package substrate 110, a chip 120, bumps 130, an underfill 140 and solder balls 150. The above-mentioned package substrate 110 has a first surface 110a and a second surface 110b, while the chip 120 is disposed between the first surface 110a and the second surface 110b of the package substrate 110. Besides, the bumps 130 are disposed between the chip 120 and the package substrate 110; and the chip 120 is electrically connected to the package substrate 110 via the bumps 130. The underfill 140 is disposed between the chip 120 and the package substrate 110 for encapsulating the bumps 130. The solder balls 150 are disposed on the second surface 110b of the package substrate 110 and electrically connected to the chip via the package substrate 110 and the bumps 130.
For a conventional flip chip package, the percentage of a material cost of the package substrate 110 over the total cost increases with the increased density of wiring layout. Besides, the internal conductive trace of the package substrate 110 is likely to be disconnected due to the shrinkage of thickness thereof. In particular, along with the continuously enhancing performance of a chip, the coefficient of thermal expansion (CTE) dismatch between the package substrate 110 and the chip 120 would gradually deteriorate the thermal stress problem.